|Working on the system clock board on the J90 backplane.|
The Central Control Unit is in the foreground.
Everything seems to be functional with one exception - there is a system clock PWR FAULT light showing on the Central Control Unit. We suspected a loose cable or board connector and traced the signal paths. We couldn't find the cause of the fault and will need to dig deeper another time.
|Checking the connections inside the CCU.|
There have been a number of problems caused by missing entries in the startup files for the IOS which prevented it from loading the mainframe configuration. Without hardware or installation documentation we resorted to tracing error messages in the log files to determine what was missing.
|Configuring the I/O Subsystem from the console.|
After a few changes the IOS recognizes the board layout including the type and number of modules in the backplane. The eight scaler/vector processors and two memory boards are now properly configured.
|J90 Mainframe hardware setup.|
The Slave IOS automatically begins loading after the Master has finished. Both IOPs run the powerup and frstload diagnostics after a power reset. These diag tests throw some errors due to the trouble with the clock board. By the end of the day the system was functional enough that we can run the individual Automated Confidence Tests from the command line. Everything internal to the IOS checks out fine.
|The I/O Processors network booting from the console.|
For our next work session we need to trace down the fault on the system clock and configure the peripherals.