|A Cray J90 quad processor module.|
The ASIC chip types are:
- MBI - DRAM memory interface
- MAD - Memory side of memory crossbar for read data
- MAR - Memory side of memory crossbar for write data
- VA - CPU side of memory crossbar for write data
- VB - CPU side of memory crossbar for read data
- CI - Channel interface (I/O)
- JS - Shared registers for multi-CPU applications
- PC - Scalar processor and processor control
- VU - Vector processor
- MC - Maintenance and clock distribution
There is only one chip (called PC) for each scalar processor and one additional chip (called VU) for each vector processor. There are only 8 chips on each processor module for the CPUs and the rest of the 18 out of 26 chips are used for communication between processors or between the processors and the memory banks. This circuitry is the key to a "balanced" system where the memory bandwidth is great enough to sustain the rate at which the processors can operate on the data.
|Silicon To Supercomputers: CRAY J90 Series ASICs|
A description of the functionality of each chip can be found in the archived version of a Cray webpage, which is linked above. The rationale for choosing ASICs for the design is detailed in IC technology and ASIC design for the Cray J90 supercomputer.
An important feature of the ASICs is the incorporation of the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture, more commonly known as JTAG. This allows running diagnostics on prototypes during design and on production chips during manufacture, and after the system is installed at a customer site. For details see the PDF document Cray Research beats the market with boundary scan.